The present invention relates to a virtual memory control multiprocessor system having a plurality of processors.
In a conventional virtual memory control multiprocessor system of this type, a translation lookaside buffer (to be referred to as a TLB hereinafter) is arranged for each processor to perform address translation from a logical address to a real address at high speed. In a system of this type, purge (initialization) of TLBs of all processors must often be performed to equalize the contents of the TLBs.
As shown in FIG. 1, in a multiprocessor system having processors 10.sub.0 through 10.sub.3, assume that the processor 10.sub.0 supplies a TLB purge request to the processors 10.sub.1 through 10.sub.3. For this purpose, the processor 10.sub.0 supplies a purge request signal la to the processor 10.sub.3. The processor 10.sub.3 performs TLB purge processing in response to the signal 1a. In this case, the processor 10.sub.0 performs its own TLB purge processing while the processor 10.sub.3 performs TLB purge processing. When TLB purge processing of the processor 10.sub.3 is completed, the processor 10.sub.3 sends back a purge end signal 2a to the processor 10.sub.0. When the processor 10.sub.0 receives the signal 2a from the processor 10.sub.3, the processor 10.sub.0 sends a purge request signal 1b to the processor 10.sub.2. The processor 10.sub.2 performs TLB purge processing in response to the signal 1b and sends back a purge end signal 2b to the processor 10.sub.0. When the processor 10.sub.0 receives the signal 2b from the processor 10.sub.2, the processor 10.sub.0 then sends a purge request signal 1c to the next processor 10.sub.1. The processor 10.sub.1 performs TLB purge processing in response to the signal 1c and sends back a purge end signal 2c to the processor 10.sub.0. When the processor 10.sub.0 receives the signal 2c from the processor 10.sub.1, the processor 10.sub.0 determines that all TLB purge operations of the processors 10.sub.0 through 10.sub.3 are completed.
In the conventional multiprocessor system described above, the TLB purge operations of the processors are sequentially performed. Assume that the time required for a given processor to receive a purge request signal, perform purge processing in response to this signal, and send back a purge end signal to the processor which has supplied the purge request signal thereto is defined as T. In this case, in the system of FIG. 1, the total time for all the TLB purge operations of the four processors 10.sub.0 through 10.sub.3 is 3T, as shown in FIG. 2. In a multiprocessor for sequentially performing TLB purge operations, TLB purge time is linearly increased in proportion to the number of processors, resulting in inconvenience.